1. Field of the Invention
The present invention relates to a VRAM (video RAM)-based parity engine for use in a disk array controller, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the present invention relates to a parity engine structure and a parity generation method, in which the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation.
2. Description of the Prior Art
In computer systems, the processing speed and reliability have been improved continuously. On the other hand, the performance of the disk storage device has been improved in slow steps compared with the main processing device, with the result that the performance difference between the two devices has been growing more and more. In order to reduce such a performance difference between the two devices, a disk array has been proposed.
In "Case for Redundant Arrays of Inexpensive Disks (RAID)" (Patterson et al., ACM SIGMOD Conference, Chicago, Ill., Jun. 1-3, 1988, pages 109-116), it was designated that the capacity of large scale disks is improved in a fast step, while the performance is improved in a slow step. In this treatise, it was proposed that inexpensive disks are formed into an array so as to use it as a large scale disk. Such redundant arrays of inexpensive disks (RAID) not only improves the performance, but also upgrades the reliability of the single large scale disk which was a conventional problem.
In a disk array controller which was devised by John G. McBride, a VRAM which is a dual-port memory is used as a buffer between a disk data path and the array controller, and provided with a counter, thereby giving a programmable capability (John G. McBride, Programmable Disk Drive Array Controller, European Patent Application No. 93110553.0, Jul. 01, 1993). In this array controller, the VRAM is used as a controllable speed matching buffer between the disk and the host interface of the array controller.
In a disk array controller and a disk array operation method which were devised by Robert A. DeMoss and Keith B. Dulac, there is used a bus switch having a parity arithmetic logic capability (Robert A. DeMoss and Keith B. Dulac, Method of operating a Data Storage Disk Array, European Patent Application No. 93308454.3, Oct. 22, 1993). In this array controller, the operation is executed always by reading the data and the parity block from the disk, and a fast parity arithmetic operation is possible on the data path by using a bus switch including a parity arithmetic logic, but the parity block cannot be cached.
In a disk controller which was devised by Dennis J. Alexander, Ryan A. Callison and Ralph S. Perry, there is carried out a parity arithmetic operation for the data which are read from a plurality of disks, by using a transfer controller and a transfer buffer RAM, while the writing performance is improved by using a posted write RAM (Deniss J. Alexander, Ryan A. Callison and Ralph S. Perry, Disk Drive Controller with a Posted Write Cache Memory, European Patent Application No. 93304372.1, Jun. 04, 1993).
In the disk array controllers of the prior art, a buffer or a parity arithmetic logic is provided on the data path, with the result that only a high speed parity arithmetic is possible, or only buffering is possible. As to the structure of the parity engine in the RAID controller of the prior art, there is internally installed a processor separately from the main processor of the controller. Therefore, either the processor carries out a parity arithmetic, or the temporary buffer which is required for carrying out the parity arithmetic includes an SRAM. As a result, the cost is high, but notwithstanding, the performance is inferior.
Further, in the case where the temporary buffer consists of an SRAM, when an XOR arithmetic is carried out for two blocks, first a block is read from the disk cache memory to store it, and then, another block of the SRAM is read, in order that an XOR arithmetic can be carried out for the two blocks. Then a writing has to be carried out into the memory. That is, in all, three accesses are necessary.